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PNIASIC

HostProcessorInterface

Host Processor Interface

All accesses to and from the PNI ASIC are through a hardware handshaking, synchronous serial interface

that adheres to the Motorola SPI protocol. The interface consists of six signals; SCLK, MOSI, MISO,

SSNOT, RESET and DRDY.

Table 8: Pin Definitions

26 DIE

(pin #)

28 MLF

(pin #)

Name

I/O

Type

Test Type

Parameters Description

1 26 VSTBY DP V

Input protection clamp diode. Connect to V

2 27 SCLK DI IBT

Serial Clock input for SPI port. 1 MHz

maximum (Rext = 100 kHz)

3 28 MISO DO OB2 Serial data output (Master In Slave Out)

4 1 MOSI DI IBA Serial data output (Master Out Slave In)

5 3 SSNOT DI IBA Active low chip select for SPI port

--- 2 Not Connected

6 4 AV

AP V

Supply voltage for analog section

7 5 AV

AP V

Ground pin for analog section

8 6 +ZDRV DO OB3 Z sensor drive output

9 7 +ZIN AI AIB Z sensor sense input

10 8 -ZIN AI AIB Z sensor sense input

11 9 -ZDRV DO OB3 Z sensor drive output

12 10 +YDRV DO OB3 Y sensor drive output

13 11 +YIN AI AIB Y sensor input

14 12 DV

DP V

Supply voltage for digital section

15 13 -YIN AI AIB Y sensor input

16 14 -YDRV DO OB3 Y sensor drive output

17 15 +XDRV DO OB3 X sensor drive output

18 16 +XIN AI AIB X sensor sense input

19 17 -XIN AI AIB X sensor sense input

20 18 -XDRV DO OB3 X sensor drive output

21 19 DV

DP V

Ground pin for digital section

--- 20 Not connected

22 21 COMP DO OB1 Comparator output. Used for diagnostics.

23 22 RESET DI IBA Rest input

24 23 DRDY DO OB1 Data ready

25 24 DHST DIO IOIA

High speed oscillator output. Output is ½

clock speed. Use for diagnostics

26 25 REXT AI AIB

External timing resistor for high speed clock.

100 k ohm typical

Exposed Paddle

(center Pad)

Connect to analog ground

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